Dillibabu Shanmugam
PhD Researcher at Vernam Lab, Worcester Polytechnic Institute. Working with Prof. Patrick Schaumont on side-channel analysis, fault injection, ASIC design, and post-quantum cryptography.
Hardware security researcher with 17 peer-reviewed publications and 14+ years of combined industry and research experience. Led two ASIC tape-outs (TSMC 180nm) and specialized in side-channel analysis (power, EM), fault injection (EMFI, laser, clock glitch), post-quantum cryptography (ML-DSA-87), and ML-based security verification.
I bridge the gap between theoretical fault models and practical hardware behavior, developing tools and methodologies for detecting, characterizing, and mitigating hardware-level vulnerabilities in embedded systems and RISC-V processors. I also work on deep learning approaches (CNN/GNN achieving 92% accuracy) for security assessment of micro-architectural states.
Fault Injection & Analysis
331 EMFI campaigns on RISC-V SoC. Direction-aware PDN loop models for fault susceptibility. EMFI, laser, and clock glitch attacks.
Side-Channel Analysis
Differential and correlation power analysis on block ciphers (AES, PRINCE, SIMON, LED, GIFT), with countermeasure evaluation.
Pre-silicon Security
Leakage assessment using pre-silicon models, scan-chain-based micro-architecture state monitoring, and early-stage vulnerability detection.
Lightweight Cryptography
Secure implementation of lightweight ciphers for IoT and resource-constrained devices, including stream ciphers and block ciphers.
ML for Hardware Security
CNN/GNN-based fault detection achieving 92% accuracy. Transfer learning reducing SCA traces by 2.8× and test time by 30%.
Security Tools & Frameworks
Co-developer of SCAPEgoat, FaultDetective, and GlitchGlück toolchains for side-channel and fault security evaluation.
ASIC Design
Full RTL-to-GDSII flow. Led 2 tape-outs (CAPRI1, CAPRI6) in TSMC 180nm using Cadence, Synopsys, and OpenROAD.
Post-Quantum Cryptography
First pre-silicon SCA methodology for ML-DSA-87 (FIPS 204): CPA with MTD=6 traces, template attacks with top-10 key recovery in 50 traces.
-
Research AssistantWorcester Polytechnic Institute — Vernam LabAug 2021 – Dec 2026 · Advisor: Prof. Patrick Schaumont · 17 papers, 2 ASIC tape-outs (TSMC 180nm), 331 EMFI campaigns, pre-silicon SCA for ML-DSA-87
-
Research InternIIT Madras, IndiaMay 2024 – Aug 2024 · Hardened cryptographic IP cores against fault attacks using formal verification and layout-aware sensors
-
Security Research InternRiscure, San Francisco, USAMay 2023 – Aug 2023 · Pre-silicon side-channel analysis on RISC-V ASIC, EM leakage identification in AES IP at layout level
-
Researcher (14 years)Society for Electronic Transactions and Security (SETS), IndiaFeb 2007 – Aug 2021 · DPA/CPA on AES, lightweight ciphers · Hardware countermeasures (masking, shuffling, redundancy) · 10 publications
- MAQAN (Co-PI) — Developed field-deployable CoW-QKD between IIT Madras and SETS. Funded by MeitY.
- DST QuEST Project (Q61: PI) — Developed Key Distillation Engine (KDE) for RPL and IITK Quantum Key Distribution systems.
- Secure Threshold Implementation (PI) — Secure threshold implementations of cryptographic primitives. Funded by MeitY.
- DDoS Detection & Mitigation — Hardware and software solutions for DDoS detection and mitigation. Funded by NTRO.
- Side-Channel Analysis — SCA evaluation of cryptographic implementations. Funded by IMSc, Chennai.
-
Ph.D., Electrical and Computer EngineeringWorcester Polytechnic Institute, MA, USAAug 2021 – Dec 2026 · Advisor: Prof. Patrick Schaumont · Focus: Hardware security, SCA, fault injection, ASIC design, ML for vulnerability analysis
-
B.E., Electronics and Communication EngineeringAnna University, IndiaJun 2001 – May 2005